Xilinx Virtual Cable (XVC) is a TCP/IP-based communication protocol that acts See the License for the specific language governing permissions and WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. Unless required by applicable law or agreed to in writing, softwareĭistributed under the License is distributed on an 'AS IS' BASIS, You may not use this file except in compliance with the License.

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Zynq®-7000 demonstration with Application Note and Reference Designs available in XAPP1251 - Xilinx Virtual Cable Running on Zynq-7000 Using the PetaLinux Tools.

Debug via Vivado Logic Analyzer IDE exactly as if directly connected to design via standard JTAG or parallel cable.

Ability to debug a system over an internal network, or even the internet.

Need to efficiently debug Xilinx FPGA or SoC systems deployed in the field to save on costly or impractical travel and reduce the time it takes to debug a remotely located system.

the JTAG pins are only accessible via a local processor interface

Do not have direct access to the FPGA pins – e.g.

Have the FPGA in a hard-to-access location, where a 'lab-PC' is not close by.

This capability helps facilitate hardware debug for designs that: Description: Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol thatĪcts like a JTAG cable and provides a means to access and debug yourįPGA or SoC design without using a physical cable.

Download virtual cable